Srilekha Gorre
Mts - Full Chip Low Power Design and Signoff @AMD
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WORK HISTORY
Mts - Full Chip Low Power Design and Signoff @AMD
Hyderabad, IN
EDUCATION
National Institute of Technology Warangal
Master's Degree, Power Electronics and Drives
University College of Engineering, Osmania University
Bachelor's Degree, Electrical and Electronics Engineering
SKILLS
ABOUT SRILEKHA GORRE
10+ years of broad technical experience encompassing Silicon power delivery, Reliability Verification (EM/IR), System integration and Platform power delivery- Specialized experience in designing and analyzing on-die power delivery solutions for server Monolithic to Disaggregated SoC’s across Intel’s 10nm, 7nm, 18A process node incorporating EMIB/Foveros/3DIC technologies- Strong leadership in cross-functional collaboration, stakeholder management, optimizing PDN from Tech readiness to Tape-in - Led IR/RV convergence for several SoC’s and also enabled A0 PRQ using innovations in execution- Postgraduate with a Master of Technology Degree in Power Electronics and DrivesTechnical skills- Adept in Power Delivery Network (PDN) Design and Analysis- Proficient in EMIR convergence - Circuit Design and Analysis Tools: Cadence Virtuoso, Ansys HFSS, HSpice/Pspice - Silicon Layout and Analysis Tools: Redhawk CPM and Redhawk SC, Synopsys ICC2, Fusion and 3DIC compiler - Programming languages: Python, tcl/shell scripting - Familiarity with Cadence project manager, orCAD capture for Schematics and Cadence Allegro® and OrCAD Layout for PCB design, MATLAB Simulink and programming.
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