Srikanth Reddy Jakkireddy

WORK HISTORY

EDUCATION

SKILLS

ABOUT SRIKANTH REDDY JAKKIREDDY

Over 7 years of experience in VLSI - ASIC domain, specifically in DFT and worked for 9 SOC projects with successful tape outs.Professional Experience: RESPONSIBILITIES:AMS• Part of the design team to enable the access to characterize the analog blocks like PLL, FLL-blocks, ADC, DAC, DCDCs on ATE.• Wrote test case for Analog block like PLLs, FLLs and mixed signal block characterization.• Worked with TE for the test program development by using techniques to reduce test time and vector memory on ATE.SCAN: • Worked on defining methodologies and implementing DFT architecture for SoC’s.• Analyzed Spyglass DFT_DRC at RTL level.• Generated EDT files at RTL level.• Implemented Block-level scan insertion.• Integration of Compression techniques to reduce ATE test time and vector size.• Test point Insertion for improving coverage.• Implemented single scan chain methodology for complete SoC.ATPG:• Generation of test patterns which includes, compressed patterns and At-Speed vectors.• Wrote testcase for Pll locking sequence and converted it into a test procedure sequence for ATPG.• Identified and analyzed areas of low fault coverage and suggested mechanisms to increase coverage.• Single Scan Chain pattern generation. IJTAG• Ijtag implementation for controlling blocks with SIB.• Development of ICL and PDL according to testcase.JTAG• Bscan implementation and verification for SoC level.• BScan implementation at IP level. i.e.lvbscan flow• DC parametric tests.STA:• Timing Constraints generation for all DFT modes.Verification:• BSCAN simulations.• AMS simulations.• RTL Simulations for MBIST.• Timing Simulations for chain, serial and parallel vectors and debugging.ATE Support:• Generation of all tester supported patterns.• Silicon bring up activities.