Srikanth Gundapu

About Srikanth Gundapu

11Yrs of Industry Experience in IP & Subsystem,SOC Verification Field.Hands on Experience on Verilog HDL and System Verilog HVL.Hands on Experience on Methodology – UVM.Having good experience on Creating Verification Components, Monitor, Scoreboard, Driver and Test Sequences, Assertion Based checker, Coverage model. Creation of Bind files.Development of Test plan and Test matrices.Worked on PCIe, NVMe, MIPI - Unipro, MIPI- UFS, Timer, PPS, GPIO Mux.Protocol: AMBA APB, AHB, I2C.Tools - QuestaSim,VCS, NCsimScripts – Perl.Worked on SOC with arm processor.

Experience

1. Senior Staff Verification Engineer

   Ambiq

   Oct 2024 — Present · TX, US

Education

• Narayana Engineering College

  Bachelor's degree, B.Tech

  2007 — 2011

Skills

• Vcs
• Assertions
• Verilog
• System on a Chip (Soc)
• Ncsim
• Rtl Coding
• Uvm
• Systemverilog
• Functional Verification
• Functional Coverage
• Universal Verification Methodology (Uvm)