Srikanth Bitla
- Role
- Pre-silicon Verification Engineer at Intel
- Location
- Warangal, IN
- LinkedIn followers
- 500 followers
About Srikanth Bitla
Experienced ASIC Design Verification Engineer with a demonstrated history of working in…
Experience
Pre-silicon Verification Engineer
Dec 2019 — Present
DDR PHY Feature Validation includes PM, DVFS, etc… Test-plans creation, Sequence/Tests coding, Assertions/Checkers coding, Regression debug and Coverage closure. Bringup DDR5, LPDDR5 technologies. JEDEC SDRAM Features Verification. Constrained Randomisation of JEDEC SDRAM and DDR PHY Parameters. Integration and feature verification support of DDR PHY IP at MCSS and SoC level. Zero Delay and SDF Gate Level Simulation setup bringup and regression closure at DDR PHY IP.
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