Srijit Misra

About Srijit Misra

14+ years of experience in - Power Delivery Architecture Design and PG Analysis- mmwave/rf and mixed-signal circuit design in integrated solutions space- Experience with transmission lines, I/O buffers and SOC interfaces- Experience with mixers, PLLs and data-converters like DACs, ADCs- Custom Analog & Mixed Signal IP Design in TSMC, GF and Samsung Foundry- Design with Verilog, Behavourial Modelling with Verilog-AMS- Physical Design, Timing Closure(STA), Parasitic Extraction, Reliability Analysis, Block Level Integration- Proficiency with Cadence Virtuoso: ADE-XL, HSPICE, Spectre, Calculator tool- Proficiency with matlab.

Experience

1. Senior Design and Analysis Engineer

   Apple

   Sep 2021 — Present · CA, US

Education

• Nava Nalanda

  +2, Science

  1993 — 2007

• North Carolina State University

  Master's degree, Electrical and Electronics Engineering

Skills

• Standard Cell Characterization
• Analog
• Reliability Checks
• Analog and Standard Cell Layout
• Cadence Virtuoso(Mmsim + Ncsim)
• Vhdl
• Timing Analysis
• Analog Circuits
• Hspice
• Cadence Virtuoso
• Analog Circuit Design and Verification
• Ams Modelling
• Signal Integrity
• Calibre
• Vhdl-Ams
• Mixed Signal
• Circuit Design
• Assura
• Static Timing Analysis
• Verilog-Ams
• Semiconductors
• C
• Vlsi
• Circuits & Electronics (Mit Certified 6.002x)
• Physical Design
• Matlab
• Atpg
• Physical Verification
• Parasitic Extraction
• Spice
• Block Level Integration
• Verilog