Sridhar Venkatesh
RTL Design Engineer at Google
- Role
- Rtl Design Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sridhar Venkatesh
RTL Design Engineer with a demonstrated history of expertise in the ASIC Front end & FPGA design to bring-up cycle. Skilled in IP design, Sub system integration, flow/methodology development, timing closure, bring up, scripting and support to verification, software teams.
Experience
Rtl Design Engineer
Jun 2025 — Present · Bengaluru, IN
Education
Madras Institute of Technology Campus
Bachelor's Degree, ECE
2011 — 2015
Skills
- Xilinx Vivado
- Verilog
- Perl
- Linux
- Flash Animation
- Sony Vegas
- Altera Quartus
- Photoshop
- C++
- Shell Scripting
- Xilinx Ise
- Timing Closure
- Management
- Fpga
- Android
- Piano
- C
- Programming
- Altera
- Xilinx
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