Sri Harsha Munagala
Silicon Architect, Google | Ex-Qualcomm | NIT-Warangal\'19
- Role
- Asic Power Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sri Harsha Munagala
Silicon Architect with expertise in Micro-Processor Architecture and SoC Power…
Experience
Asic Power Engineer
May 2024 — Present · Bengaluru, IN
Awarded 3xPeer bonus and 2xSpot Bonus - Memory Silicon Architect, responsible for the end-to-end power design process, including power budgeting at concept phase, development of SoC power modeling tool using Python to project system level use case power post project inception and correlation of memory path components power in post-silicon- Define test cases (PtPx vector) for pre-silicon and post-silicon power validation, analysis and improve accuracy of power model- Analyze and monitor power estimates from PtPx vector throughout the SoC design process to achieve the power goals- Collaborate with architecture, Design and Implementation teams to evaluate and optimize power management architecture of SoC with specific focus on Memory Path Components.
Education
National Institute of Technology Warangal
BTech - Bachelor of Technology
2015 — 2019
Sri Chaitanya Junior College, Bhaskar Bhavan
High School Diploma
2013 — 2015
Ravindra Bharathi Public School
Middle School Diploma
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