Sri Hari B.

About Sri Hari B.

Physical Design Engineer with ~2 years of experience in ASIC backend design.Skilled in placement, CTS, routing, STA, and timing closure using Innovus, ICC2, and PrimeTime.Experienced in resolving timing violations, congestion optimization, and physical verification

Experience

1. Physical Design Engineer

   Wipro

   Jun 2024 — Present · Bengaluru, IN

   Working as a Physical Design Engineer with hands-on experience in ASIC physical design and backend implementation.• Performed standard cell placement with focus on utilization, timing optimization, and congestion reduction• Implemented Clock Tree Synthesis (CTS) and optimized clock skew, latency, and insertion delay• Executed routing and resolved DRC violations to achieve clean physical signoff• Analyzed and fixed setup and hold timing violations across corners using STA (PrimeTime)• Performed ECOs for timing closure and design optimization• Identified and resolved congestion hotspots to improve routing quality• Performed IR drop and power analysis to ensure design reliability• Involved in physical verification including DRC and LVS checks• Tools: Cadence Innovus, Synopsys ICC2, PrimeTime• Automated repetitive design tasks using TCL scripting

Education

• State Board of Technical Education and Training

  Diploma, Electronics and Communications Engineering

  2017 — 2020

• JNTU Anantapur

  Bachelor of Technology - BTech, Electronics and Communications Engineering

  2020 — 2033

• Seventh-day Adventist High School

  10th, SSC

  2016 — 2017