Sri Divya Vuyyala
Design verification Engineer
- Role
- Design Verification Engineer at Capgemini Engineering
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sri Divya Vuyyala
I am very passionate about my career. I challenge myself with new technologies. My objective is to excel Wherever I work in. Strong in Digital electronics. Good knowledge in RTL coding using verilog. Good knowledge in Functional verification. Experience in writing testbenches using system verilog & UVM methodology. Good knowledge in Assertion based verification, Constrained random verification, Coverage driven verification. Experience in using industry standard EDA Tool for front end design andVerification. Basic idea on PERL. Good knowledge in Windows, Linux.Experience in Synopsys Vcs,Xilinx vivado.Protocols: APB, I2C, SPI, UART
Experience
Design Verification Engineer
Aug 2022 — Present · Hyderabad, IN
Education
Gayatri Vidya Parishad College of Engineering (Autonomous)
Bachelor of Technology, Electrical, Electronics and Communications Engineering
Sri Chaitanya Junior College
High School Diploma, M.P.C
2018 — 2018
Sri Chaitanya Techno School, Hyderabad
High School Diploma
2016 — 2016
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