Sreya S R

About Sreya S R

Standard cell characterization engineer (from 2017)*Experience on tech nodes 40nm, 45nm, 50nm and 55nm*Worked on Standard Cell Characterization and other EDA views such as celtic, redhawk, diesel, fastscan etc.Memory Circuit Design and Layout Engineer(20••••16)Got trained in various aspects of Memory IP development.* Memory Characterization and Circuit Designing- Memory Bitcell (SRAM & RF) and Sense Amplifier analysis- Memory Architecture & Critical Path Modelling- Timing, Power and Leakage Analysis of vanilla Custom and Compiler memories- Perl and Shell Scripting for various Automation requirements- DFT and power gating implementation- Tools used : Ltspice, EMC ( Embedded Memory Compiler - Zia\'s Compiler Platform )* Memory Layout- Layout leafcell development of various sub-blocks inside custom and compiler memories- Various physical verification such as LVS, DRC checks- Tools used : Glade Layout Editor, EMC Compiler Platform* Automation- Compiler coding for Netlist generation- Perl and Shell scripting for internal automation requirements- Tools used : EMC Compiler Platform

Experience

1. Component Design Engineer

   Intel

   Jan 2022 — Present · Bengaluru, IN

Education

• GOVT COLLEGE OF ENGINEERING, BARTON HILL

  Bachelor of Technology (BTech), Electrical and Electronics Engineering

  2011 — 2015

• Government Engineering College, Barton Hill, Thiruvananthapuram

  Bachelor of Technology (BTech), Electrical and Electronics Engineering

  2011 — 2015

Skills

• Standard Cell Characterisation
• Layout Design
• Register File
• Microsoft Office
• Ltspice
• Glade
• Powerpoint
• Microsoft Excel
• Memory Design
• Standard Cell
• Matlab
• English
• Design Rule Checking (Drc)
• Cmos
• C
• Programming
• Electrical Engineering
• Very-Large-Scale Integration (Vlsi)
• Simulink
• Autocad
• Layout Versus Schematic (Lvs)
• Netbeans Platform
• Linux
• Perl
• Sram
• Cadence Virtuoso
• Microsoft Word
• Electronics
• Memory Characterization