Sreekanth G Pai
DFT Engineer at Marvell India
- Role
- Senior Principal Engineer at Marvell Technology
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sreekanth G Pai
Expertise in various aspects of Test - MBIST, SCAN, ATPG, Diagnosis | Involved in tapeout of designs across various tech nodes (32 nm to 5 nm)| Execution & Methodology Development Have prior experience in functional verification (OVM)
Experience
Senior Principal Engineer
May 2025 — Present
Education
Rajagiri School of Engineering and Technology
Bachelor of Technology (B.Tech.), Applied Electronics and Instrumentation
2003 — 2007
College of Engineering Trivandrum
Master of Technology (M.Tech.), Signal Processing
2010 — 2012
Skills
- Cadence Encountertest
- Mbist
- Boundary Scan
- Asic
- C
- Verilog
- C++
- Systemverilog
- Scan Insertion
- Latex
- Modelsim
- Debugging
- Eda
- Jtag
- Dft Methodology
- Tcl-Tk
- Digital Image Processing
- Unix
- Open Verification Methodology
- Digital Signal Processing
- Rtl Compiler
- Dft
- Matlab
- Vhdl
- Testing
- Vlsi
- Application-Specific Integrated Circuits (Asic)
- Rtl Verification
- Tcl
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