Sreenivas Mandava
Intel Fellow, Datacenter Memory Controller
- Role
- Intel Fellow at Intel
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Sreenivas Mandava
Expert in integrated memory controllers for datacenter, memory protocols for direct connect memory and buffered memory, RAS features, performance tuning and DFx capabilities. Design Lead on memory controllers that support HBM*, LPDDR*, DDR4, DDR5, MRDIMM and Optane Persistent Memory. Industry expert for Row Hammer mitigation techniques. Co-inventor of pTRR and other industry schemes for row hammer mitigation. Experience in power management design, system and tester debug, and performance validation for server products.
Experience
Intel Fellow
Dec 2021 — Present
Education
University at Buffalo
M.S.
1995 — 1997
Skills
- Ddr3 Ddr4
- Semiconductors
- Static Timing Analysis
- Rtl Design
- Vlsi
- Debugging
- Soc
- Computer Architecture
- Systemverilog
- Crystal Ridge
- 3d Xpoint
- Processors
- Server Memory Controllers
- Verilog
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