Sreenithi Arul
VLSI |FPGA|IP verification engineer @capgemini .bangalore| verilog| SV|UVM
- Role
- Design Verification Engineer at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Feb 2022 — Present · Bangalore Urban, IN
working in DV role with experience of 2yearsat capgemini engineering, bangaloregood knowledge in DFx. experience in debuggingextensive skills in verilog, system verilog, funtional coverage.
Education
St. Joseph's Matriculation Higher Secondary School
10th
2012 — 2013
Er. Perumal Manimekalai College of Engineering
B. E
2015 — 2019
St. Joseph's Matriculation Higher Secondary School
12th
2013 — 2014
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