Garlapati Sreeja
VLSI Engineer
- Role
- Physical Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Garlapati Sreeja
I am Sreeja Garlapati, a highly motivated and detail-oriented VLSI Engineer with a strong academic foundation and hands-on experience as digital design engineer. I am also proficient in tackling challenges in RTL-to-GDSII design flows, including floor planning, STA, and schematic-to-layout verification. My passion is about optimizing design performance, power, and area (PPA) while leveraging scripting and automation tools.I was awarded the Gold Medal for Excellence during postgraduate studies and recognized with \"Best Paper Award\" for contributions to low-power design techniques. Being a proactive learner, I am ready to apply technical knowledge and problem-solving skills to deliver innovative solutions in the semiconductor industry.
Experience
Physical Design Engineer
Jul 2025 — Present · Bengaluru, IN
Education
Manipal Institute of Technology
Master of Technology - MTech, Microelectronics
Matrusri Engineering college
Bachelor of Engineering - BE, electronics and communication
2017 — 2021
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