Sreedeep Venkatesh

Experience

1. Senior Staff Engineer

   Qualcomm

   Sep 2024 — Present · Bengaluru, IN

   As a Senior Staff STA Design Engineer at Qualcomm, lead timing teams to drive full-chip STA closure and sign-off across complex SoCs in Mobile, Automotive, and Compute domains. Responsibilities include validating timing constraints, resolve timing issues, and implement ECOs using advanced EDA tools, ensuring optimal PPA across cutting-edge technology nodes.

Education

• Vellore Institute of Technology

  Master of Technology (M.Tech.), VLSI DESIGN

  2009 — 2011

• Sree Vidyanikethan Engineering College

  B-Tech, Electrical and Electronics Engineering

  2005 — 2009

Skills

• Eda
• Rtl Design
• Fpga
• Asic
• Vhdl
• Vlsi
• Rtl Coding
• Tcl
• Xilinx
• Systemverilog
• Verilog
• Specman
• Uvm
• Vmm
• Very-Large-Scale Integration (Vlsi)
• Primetime
• Logic Synthesis
• Amba Ahb
• Static Timing Analysis
• Ncsim
• Low-Power Design
• Formal Verification
• Arm
• Cadence Virtuoso
• Physical Design
• System on a Chip (Soc)
• Modelsim
• Functional Verification
• Drc
• Integrated Circuit Design
• Logic Design
• Open Verification Methodology
• Soc
• Timing Closure