Sravya Peddireddy

About Sravya Peddireddy

Involved in implementing GLN to GDS convergence for small ASIC. Well trained in ASIC PD flow involving Design Planning, Floor Plan, Placement and routing, Extraction, Timing Closure and Physical Verification. Experience in using tools like Synopsys (IC Compiler, PrimeTime), Mentor Graphics (Caliber, IC Studio). Through knowledge of PD concepts like Liberty, MCMM, OCV, DFT, Blockages, CTS, Core utilization, SDC, TLU+ and Signal Integrity. Have ability to resolve reliability issues like IR Drop Analysis, Congestion, Cross-talk, EM, Antenna effect, DFM and OPC. Analytical skills of Pre-layout and Post-layout STA reports. Basic awareness in scripting languages like PERL and Tcl for automation. Have knowledge on IC fabrication process, MOS technology, CMOS concepts and Digital Design.

Experience

1. Graphics Hardware Engineer

   Intel

   Jan 2017 — Present · Bengaluru, IN

   Involved in implementing GLN to GDS II convergence for advanced technologies. Excellent knowledge in ASIC PD flow involving Design Planning, Floor Plan, Placement, CTS, Routing, Extraction, Timing Closure and Physical Verification. Experience in using tools like Synopsys (IC Compiler, PrimeTime), Mentor Graphics (Caliber, IC Studio). Thorough knowledge of PD concepts like MCMM, OCV, Blockages, Core utilization, SDC and Signal Integrity. Having the ability to resolve reliability issues like IR Drop Analysis, Congestion, Cross-talk, EM, and Antenna effect, Physical verification (DRC, LVS and DFM). Analytical skills of Pre-layout and Post-layout STA reports. Basic awareness in scripting languages like PERL and Tcl for automation. Have knowledge on MOS technology, CMOS concepts and Digital Design

Education

• JNTU ANANTAPUR

  M.Tech, VLSI; ECE

  2009 — 2011

• Board of Secondary Education

  SSC

  2001 — 2002

• RV VLSI Design Center, Bengaluru.

  PG DIPLOMA, ASIC Physical Design

  2015 — 2016

• Board of Intermediate

  INTERMEDIATE, MPC

  2002 — 2004

• JNTU Hyderabad

  Bachelor in Technology (B.Tech), Electronics and Communication Engineering.

  2004 — 2008

Skills

• Cmos
• Floorplanning
• Tcl
• Vhdl
• Linux
• C++
• Application-Specific Integrated Circuits (Asic)
• Very-Large-Scale Integration (Vlsi)
• C
• Microsoft Office
• Vlsi
• Rtl Design
• Integrated Circuit Design
• Static Timing Analysis
• Synopsys Tools
• Logic Design
• Microsoft Word
• Verilog
• Physical Design
• Synopsys Primetime
• Perl