Sravani Pemmasani
FPGA Engineer
- Role
- Fpga Design Engineer at Cyient
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sravani Pemmasani
Good day! Iam having knowledge on design and verification field. in that I learnt verilog, vhdl(hdl Languages),system verilog ( hvl language), FPGA designing with static timing analysis, universal verification methodologies (UVM),and protocols( UART,SPI,I2C,AXI STREAM,AMBA APB)!
Experience
Fpga Design Engineer
Mar 2026 — Present · Hyderabad, IN
Education
Dr.kkr's Goutham concept school
10th, State
2012 — 2013
Jawaharlal Nehru Technological University, Kakinada
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2015 — 2019
Sri Vivekananda Junior College
12th, Mpc
2013 — 2015
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