Sravan Kumar

About Sravan Kumar

16 years of professional experience in building teams and driving cutting edge projects in VLSI domain. Developing verification plan for testing the features of a given module Developing OVM based Verification Environment Developing BFM based on OVM Methodology and System Verilog Developing Functional Coverage Models and assertions Functional Verification of digital blocks in Voltage Regulator IP Developing Perl scripts on need basis Developing behavioral models for analog blocks with little support from the design engineer as I have good fundamentals in analog concepts as wellMethodologies: OVM, UVMLanguages : System Verilog, Verilog HDL, C, C++EDA tools : Synopsys VCS Simulator, Model sim Questa version 10.1c, Cadence Virtuoso ADE, ADEXLscripting languages: Perl

Experience

1. Co-founder

   Micromonks Technologies

   Apr 2025 — Present · Hyderabad, IN

Education

• Indian Institute of Technology, Roorkee

  MTech, VLSI Design

  2008 — 2010

• Jawaharlal Nehru Technological University

  Bachelor's Degree, Electronics and Communication Engineering

  2004 — 2008

Skills

• Perl
• Eda
• Very-Large-Scale Integration (Vlsi)
• Integrated Circuit Design
• Systemverilog
• Analog Circuit Design
• Functional Verification
• Rtl Design
• Vlsi
• Modelsim
• Verilog
• Debugging
• Asic
• C
• Cadence Virtuoso
• Digital Circuit Design
• Open Verification Methodology
• System Verilog
• Perl Scripting
• Ovm