Sravan Kumar
RTL Design and Verification Trainee with expertise in Verilog, SystemVerilog, UVM
- Role
- Rtl Design and Verification Trainee at Vlsi First
- Location
- Hyderabad, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sravan Kumar
As an RTL Design and Verification Trainee at VLSI FIRST, I apply my skills in Verilog…
Experience
Rtl Design and Verification Trainee
Jul 2024 — Present · Hyderabad, IN
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