Spandan Das
SoC Design Verification Engineer @Intel | MS Electrical Engineering @Columbia University | Ex Cadence Design Systems | RTL Design/Validation/Computer Architecture/Functional Safety
- Role
- Design Verification Engineer at 英特尔
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Spandan Das
I am intrigued by the billions of interconnections on the nanoscale which enable a tiny…
Experience
Design Verification Engineer
May 2022 — Present · Santa Clara, CA, US
Education
Columbia University in the City of New York
Masters
2021 — 2022
Manipal Institute of Technology
Bachelor of Engineering - BE
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