Sowjanya Mareddy
Design Verification Engineer at UST
- Role
- Design Verification Engineer at UST
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sowjanya Mareddy
Currently employed as Design Verification Engineer at UST, Bangalore.Completed Professional training in Advanced VLSI Design and Verification at Maven Silicon, Bangalore.Engineering professional with a Master of Technology(M.Tech) focused in VLSI Design from VIT University.A highly optimistic personality who believes that everyone is capable to do anything, if only complete dedication and belief in oneself is maintained all through. Programming Skills: Verilog | System Verilog | Basics of C | PerlMethodology: Universal Verification MethodologyEDA Tools: QuestaSim | Xilinx ISE | Cadence Tool | Synopsis | Model Sim | Altera(Quartus II) Domain Skills: RTL Designing | RTL Design Verification using SV | Verification | Assertion based Verification OS Knowledge: Linux | Windows
Experience
Design Verification Engineer
Oct 2021 — Present · Bangalore Urban, IN
Education
Kiran English Medium High School
S.S.C
VIT_Vellore Institute of Technology
Master of Technology - MTech
Jawaharlal Nehru Technological University,Ananthapur
Bachelor of Technology - BTech
Sri Chaitanya junior college,Tirupathi
Intermediate
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