Sourav Chakravarty

Sr. Principal Engineer and Sr. Director at Intel Corporation responsible for New Product Introduction (NPI), yield improvement, and post-silicon performance optimization of Intel products on external foundry nodes.

Role
Sr Principal Engineer and Sr Director, Npi, Yield Improvement and Post-si Performance Optimization at Intel
Location
Portland, OR, US
LinkedIn followers
500 followers

About Sourav Chakravarty

Experienced Senior Technology Engineer with a demonstrated history of working in the semiconductors industry. Presently responsible for NPI (New Product Introduction), Yield improvement, and post-Silicon performance optimization of Intel products on external foundry nodes. Demonstrated technical leadership being the primary Post-Si Engineering interface with all external foundries and leads a 2-level team of talented Product, Yield, and Software engineers. Also skilled in technology definition through large scale Power, Performance, Area optimization and analysis of ASIC blocks, Machine Learning application to automate and reduce throughput time in pre-Si and post-Si ASIC implementation, and Collaboration with EDA vendors and external IP partners to improve ASIC implementation efficiency. Strong people managing skillset with a Ph. D focused in Electrical Engineering from Penn State University.

Experience

  1. Sr Principal Engineer and Sr Director, Npi, Yield Improvement and Post-si Performance Optimization

    Intel

    Jul 2021 — Present · Hillsboro, OR, US

Education

  • Penn State University

    Ph. D, Electrical Engineering

    1997 — 2001

  • National Institute of Technology Kurukshetra

    B. Tech, Electronics and communication

    1988 — 1992

  • Jadavpur University

    M.Tech, Electronics and Telecommunication

    1995 — 1997

  • Sri Vidya Mandir High school

    10th Std.

    1976 — 1986

  • St. Joseph's college of arts and sciences

    12th std, Science

    1986 — 1988

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Sourav Chakravarty — Sr Principal Engineer and Sr Director, Npi, Yield Improvement and Post-si Performance Optimization at Intel in Portland, OR, US | Unifers