Sourabh G.
Rtl Design Engineer @Apple
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WORK HISTORY
Rtl Design Engineer @Apple
EDUCATION
Delhi College of Engineering
BE, Electronics and Communications Engineering
Dev Samaj Modern School
High School, Science Stream
ABOUT SOURABH G.
Experience in full flow IP design (Micro-Arch and RTL) and SoC integration activities (Micro-Arch and IP integration) ranging from managing a small team to part of large teamSpecialties(Expert): AXI, AHB, LPDDR4, Verilog, System Verilog, Python, Lint, CDC, UPF, Timing Constraints, Timing report analysis, Simulation Debug, Post-Si Debug, Verfication Testplan creation, UPF, Emulation Debug.Past - PCI, PCIe, QuadSPI flash controller, CDC, IPXACT, I2S, I2C DMA, SMBusTools - QuestSim, VCS, SpyglassLP/CDC/Lint, LEC,
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