Unifers.ai

Souda T. K

Memory Layout Engineer

Role
Memory Layout Engineer at Intel
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

About Souda T. K

M.Tech with 15+ years of Analog and Memory Layout experience in Intel, ARM, Qualcomm and Synopsys.• Currently working as Layout Design Engineering Manager at IntelCore Competencies•Analog & High-Speed IP (UCIe-A, Chip2Chip) Layout & Verification•Memory Compiler & Full-Custom Memory Layout & Verification•FinFET & CMOS Technologies (3nm, 7nm, 10nm, 12nm, 16nm, 22nm, 28nm, 40nm, 90nm, 180nm)•Engineering Team Leadership & Mentoring•Project Planning & Execution•Performance Reviews & Talent Development•Cross-functional & Global Team Collaboration•Stakeholder Management & Technical Reporting

Experience

  1. Memory Layout Engineer

    Intel

    Jul 2025 — Present

Education

  • Kannur University, LBS College of Engg Kasaragod Kerala

    B.Tech

    1999 — 2003

  • Dr M.G.R University

    M.Tech

    2005 — 2007

Skills

  • Sram
  • Cadence Virtuoso
  • Drc
  • Hercules
  • Lvs
  • Vlsi
  • Cmos
  • Physical Verification

Find verified contacts for anyone on LinkedIn

Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.

Start for freeSee how it works

Free plan included · No credit card required

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.

Souda T. K — Memory Layout Engineer at Intel in Bengaluru, KA, IN | Unifers