Sooraj Chandra

About Sooraj Chandra

ASIC Design engineer with hands on experience on high speed protocols like PCIe, Ethernet, CPRI, JESD204C. Micro-architecture, RTL Design, Linting, STA, CDC, Power optimization, FPGA Prototyping, Emulation.

Experience

1. Senior Asic Rtl Design Engineer

   NVIDIA

   Jul 2022 — Present · Bengaluru, IN

   PCI Express (PCIe) ASIC / RTL DesignMicro-architecture• Contributed to PL data path micro-architecture till latest PCIe Generation (1b1b)• Worked on area latency and timing optimization for replicated logic across multi-lanes and multi-link architectures.• Contributed to Flit Mode L0p micro-architectureRTL Design• Worked on multiple receive side components like L0p feature, Lane-to-Lane De-Skew, Ordered Set Decoders, PL and Data Link Layer Error reporting, Design for debuggability (DFD), Polling Compliance• Good experience working with LTSSM, Equalization, and PHY - PL - DL interactionDesign Quality-•Timing path optimization (STA) and design optimization with adding pipelines or by design optimization and making design parallel and wider.• Clock Domain Crossing (CDC) analysis for complete IP• Power Analysis analysis for complete IP and adding FGCG, and higher (second/block) level Clock Gates.• Analyzed Formality, Linting (spyglass), and Code Coverage.Post-Silicon IP Bring-up:• Inter-operation with other devices like retimers, PCIe Switches, various Root Port Devices, Endpoint devices, FPGA based Exercisers.• Contributed to various setups including root port devices, PCIe Switches, retimers and multiple endpoint devices. Peer-to-peer communication between two endpoint devices.• Came up with test plan, Worked on Equalization, PHY parameters tuning, Full Bandwidth utilization testing, Low power ASPM/PCI-PM, complete LTSSM and PERST checkout• PCIe FW testing.• Link up to full feature checkout including traffic testing Flit mode and Non Flit Mode.• Thorough experience working with Out-of-band accesses like I2C and JTAG. Other Activities-• Supporting the Formal Verif team and reviewing constraints, coordinating with the Design Verification team during testplan creation, initial simulation bring up and triaging and debugging issues during chip tapeout.• Supporting FPGA and Emulation bringup. Assisting with initial PCIe FW settings and programming

Education

• Delhi College of Engineering

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering