Sonika M

Physical Design Engineer @Chipsil Technologies Pvt Ltd

Hyderabad, IN

As a Physical Design Engineer trainee, I\'m responsible for implementing ASIC Physical Design Flow from Importing Design, performing Sanity Checks, Floorplan, Powerplan, Placement, CTS and Routing using Fusion Compiler and IC Compiler. My responsibilities included writing ECOs for fixing DRVs in Prime Time. Worked on timing analysis and fixed slack and DRVs (Max Tran, Max Cap). Optimized 2 block level designs for better PPA.Worked on Synopsys Tools- ICC2 Compiler, Fusion Compiler and PrimeTime

RestartHer Academy

Self Development/ Career Restart , Soft Skills

Bhashyam EM High School

SSC, High School/Secondary Diplomas and Certificates

Narayana Junior College - India

Intermediate, MPC

Aditya Educational Institutions

Bachelor of Technology, Electronic and Communication Engineering

St.Joseph's Public School (ICSE Syllabus)

Upto 5th Standard, Primary Schooling