Sonika M
Physical Design Engineer | Static Timing Analyst | Passionate about Advancing My Career in VLSI – Physical Design - STA | Driven to Contribute to Cutting-Edge Technology and Innovation
- Role
- Physical Design Engineer at Chipsil Technologies Pvt Ltd
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sonika M
Senior Physical Design & STA Engineer | SDC & Timing Closure | AI-Driven…
Experience
Physical Design Engineer
Jul 2024 — Present · Hyderabad, IN
As a Physical Design Engineer trainee, I\'m responsible for implementing ASIC Physical Design Flow from Importing Design, performing Sanity Checks, Floorplan, Powerplan, Placement, CTS and Routing using Fusion Compiler and IC Compiler. My responsibilities included writing ECOs for fixing DRVs in Prime Time. Worked on timing analysis and fixed slack and DRVs (Max Tran, Max Cap). Optimized 2 block level designs for better PPA.Worked on Synopsys Tools- ICC2 Compiler, Fusion Compiler and PrimeTime
Education
RestartHer Academy
Self Development/ Career Restart , Soft Skills
Bhashyam EM High School
SSC, High School/Secondary Diplomas and Certificates
2010 — 2015
Narayana Junior College - India
Intermediate, MPC
2015 — 2017
Aditya Educational Institutions
Bachelor of Technology, Electronic and Communication Engineering
2017 — 2021
St.Joseph's Public School (ICSE Syllabus)
Upto 5th Standard, Primary Schooling
2004 — 2010
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