Somya Dashora

About Somya Dashora

Currently building RISC-V IOMMU at Ventana!**Design Engineer with experience in architectural research, design & development of RTL IPs. I have worked on micro-architecture design for Processor Core based on the open RISC-V ISA. Gained strong analytical, management, debugging and problem solving skills along with strong command over HDL & scripting languages. Initiative driven, team player; I thrive well in fast-paced work environment.During my professional experience, I have developed a strong understanding of RTL Design, Development, and Implementation of digital circuits. I have worked on the design and development of a L1 Instruction Cache, a RISCV Sv39 & Sv39x4 based Memory Management Unit, and successfully led a team to architect, develop and validate a RV64GCBHSU based multi-threaded core.Additionally, I have assessed and implemented micro-architecture design strategies aimed at enhancing performance and power efficiency. I have good knowledge of the interaction between Hardware & Software, Virtualization, and Hypervisors. I have gained extensive exposure to industry standard EDA tools and processes used for IP development, as well as tools and techniques for project management, version control and workflow automation. I also have working knowledge about Functional Safety processes, tools and micro-architectural techniques for reliability.I am enthusiastic about working on diverse design aspects of architectures/IPs, including but not limited to IOMMU’s, Virtualization for Accelerators & DMA Engines, SIMD/Vector Architectures, UCIe & D2D controllers, Hardware assisted garbage collection for JIT languages, Compression Engines in Memory Hierarchy etc.https://github.com/somyadashora

Experience

1. Staff Engineer

   Qualcomm

   Dec 2025 — Present

Education

• Maharana Pratap University of Agriculture and Technology

  Bachelor's degree, Electronics and Communication

  2013 — 2017

• Center for Development of Advance Computing, PUNE

  PG DIPLOMA , VLSI

  2018 — 2018