Someswara Rao Althi
Physical Design Integration Engineer
- Role
- Physical Design Integration Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Someswara Rao Althi
Hands-on experience in ASIC Block level Physical Design Flow (Netlist to GDSII)- Floor planning, Placement, Clock Tree Synthesis, Routing and ECOs using FC, ICC2 and PT.Full chip Physical Verification – Integrating the blocks and fixing Antenna, Density, DRC and LVS etc.Working experience with lower technology nodes 18A, intel-3, intel-16, 7nm, 10nm, 12nm and 14nm Working on LVS, DRC, density, antenna fixes, base and metal layer DRCs, RV fixes(EM, IR drop, etc.) & Routing in different challenging conditions using ICC, ICC2 & ICV tools. ECO implementation (Buffer insertion, Cell sizing, Swapping, Net detouring to meet timing).
Experience
Physical Design Integration Engineer
Oct 2021 — Present · Bengaluru, IN
Physical Design- Block levelLead and Full chip level Physical Verification
Education
SRMIST, Kattankulathur, Chennai ,Tamil Nadu
Master of Technology (M.Tech.), VLSI design
2015 — 2017
Andhra University
Bachelor of Engineering (BE), electronic and communication engineering
2011 — 2014
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.