Sneh Shah
Sr Staff Design Verification Engineer at Marvell Technology
- Role
- Sr Staff Design Verification Engineer at Marvell Technology
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Sneh Shah
Experienced Verification Engineer with a demonstrated history of working in the ASIC and NAND industry. Strong quality assurance professional skilled in Universal Verification Methodology (UVM), SystemVerilog, Python, Application-Specific Integrated Circuits (ASIC) and RTL Verification.
Experience
Sr Staff Design Verification Engineer
Dec 2021 — Present
Machine Learning
Education
Santa Clara University
Master of Science (M.S.), Electrical and Electronics Engineering
2011 — 2013
University of Southern California
B.S., Electrical Engineering
2008 — 2011
Skills
- Verilog
- Asic
- Systemverilog
- Fpga
- Dft
- Functional Verification
- C++
- Uvm
- Verification
- Rtl Verification
- Low-Power Design
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