Snehal Jariwala
Sr. Principal Engineer/Sr. Manager - Display Engineering
- Role
- Principal Engineer Sr Manager Display Architecture at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Snehal Jariwala
Technical leader with 25+ years experience of successfully delivering System architecture, Display Module Design as well s Mixed-Signal IP blocks covering industry standard SerDes, DDRs, Display IPs including LVDS/HDMI and DAC as well as ADCs from specification to High Volume Manufacturing for Intel\'s Client, Server, Phones, Tablets and Consumer SoC product lines on Intel technologies. Leader with direct experience of managing Product Requirements, IP Architecture, Execution of Logic/Circuit/SD/Layout and Post Silicon Debug, Logo testing and certification.
Experience
Principal Engineer Sr Manager Display Architecture
Jun 2021 — Present · Cupertino, CA, US
Education
National Institute of Technology Surat
BS
1989 — 1993
University of Southern California
MS
1997 — 1998
Florida Institute of Technology
MS
1996 — 1996
V.D.Desai (wadiwala) School
High School Diploma
1983 — 1989
Skills
- Eda
- Physical Design
- Ic
- Application-Specific Integrated Circuits (Asic)
- Asic
- Management
- Semiconductors
- Low-Power Design
- Vlsi
- Rtl Design
- Electrical Engineering
- Sata
- Mixed Signal
- Hdmi
- Embedded Systems
- Integrated Circuits (Ic)
- Very-Large-Scale Integration (Vlsi)
- Analog Circuit Design
- Analog
- Microprocessors
- Soc
- Processors
- Field-Programmable Gate Arrays (Fpga)
- Dft
- Verilog
- Debugging
- Pcie
- System on a Chip (Soc)
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