Sneha Jadhav
Fpga Design Engineer @Jio Platforms Limited Jpl
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WORK HISTORY
Fpga Design Engineer @Jio Platforms Limited Jpl
Bengaluru, IN
5G - NR Physical Layer Developer
EDUCATION
Visvesvaraya Technological University
Bachelor of Engineering - BE, Electronics and Communications Engineering
Visvesvaraya Technological University
M.Tech , VLSI Design and Embedded Systems
ABOUT SNEHA JADHAV
FPGA Design Engineer with 6.5+ years of hands-on experience in designing and developing 5G NR physical layer modules. Skilled in RTL design, simulation, synthesis, and integration on Xilinx and Intel FPGA platforms.Proficient in Verilog/System Verilog, with strong knowledge of digital signal processing and 3GPP specifications. Completed specialized training in VLSI Design and Verification, with a solid foundation in ASIC/FPGA flows. Strong engineering professional with a Master of Technology (M.Tech.) focused in VLSI Design & Embedded Systems from Visvesvaraya Technological University(VTU), Belgaum.
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