Sunil Madhava Pai

About Sunil Madhava Pai

16yrs experience in Analog/ Mixed Signal Circuit Design, Validation for High Speed SerDes/ PHY IPs like Ethernet, CEI, USB, MIPI DPHY/CPHY. Gained experience in Wideband Transmitter Driver & Receiver Analog Front-end (CTLE, DFE) & Low Jitter High- Frequency Clocking & LDO, Bias Circuits.Worked & Interested in designing Analog Circuits for : •High Speed IO/SerDes - CEI/Ethernet/USB/PCIe/MIPIPower Management - LDO, V/I Reference Generator, Const-gm BiasClocking Mechanisms - Phase Interpolator, Duty-cycle Correction, Jitter filteringData Conversion - SAR-ADC, R2R/Flash DAC

Experience

1. Senior Principal Design Engineer

   Cadence

   Oct 2023 — Present · Bengaluru, IN

   Working in High Speed Memory Interfaces

Education

• University of Calicut

  B.Tech, Electronics & Communication Engineering

  2002 — 2006

• Kendriya Vidyalaya

  School, Science

  1996 — 2002

• SRM IST Chennai

  M .Tech, VLSI Design

  2009 — 2011

Skills

• Asic
• Adcs
• Mixed Signal
• Circuit Design
• Vhdl
• Simulations
• Application-Specific Integrated Circuits (Asic)
• Cadence Virtuoso
• Integrated Circuit Design
• Modelsim
• Pcb Design
• Verilog
• Spice
• Cmos
• Vlsi
• Analog
• Analog Circuit Design
• Very-Large-Scale Integration (Vlsi)