Smit Ashvinkumar Patel
A&MS Layout Design Engr, Sr II at Synopsys Inc
- Role
- a & Ms Layout Design Engr, Sr Ii at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Smit Ashvinkumar Patel
I aspire for challenging position in Analog & Mixed Signal Layout Design where I can employ my technical skills, learn new things and work towards Organization goal that offers Professional growth.CORE COMPETENCY Hands on experience with advanced technology nodes like 5nm, 7nm, 16nm, 28nm, 40nm, 55nm & 90nm Experience in Layout Design of High Speed SERDES IP such as Transmitter (TX), Receiver (RX) and Common Module (CM) Hands on experience in LEF, SPEF Generation Flow and GDSII Release Procedure (TX, RX & CM) Experience in A & MS Layout Design, Memory Layout Design and Standard Cell Layout Design Experience in Analog Matching Techniques, High Speed Clock Routing, Power Routing with EM/IR Consideration, Signal Shielding and IP Level Routing Practical knowledge of IC verification terminologies like DRC, LVS, ERC and Parasitic Extraction Familiar with reliability issues such as EM/IR drop, Latch-up and Overvoltage failure Understanding of DFM considerations such as antenna effect, density checks, via doubling and signal integrity Familiar with deep submicron effects like WPE, STI, LOD and OPC Hands-on experience on different tools like - Virtuoso (Cadence), IC Custom Compiler (SYNOPSYS),Helic (Inductor Generation and Extraction) and ICV & Calibre for DRC/LVS/PEX
Experience
a & Ms Layout Design Engr, Sr Ii
Jan 2024 — Present · Bengaluru, IN
Education
Nirma University
Master of Technology (M.Tech.), Electrical, Electronics and Communications Engineering
2013 — 2015
Shankersinh Vaghela Bapu Institute of Technology
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering
2009 — 2013
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