Saket Yadav
Senior Product Validaton Engineer at Cadence Design System
- Role
- Product Validation Engineer Ii at 铿腾设计系统公司
- Location
- Delhi, IN
- LinkedIn followers
- 500 followers
About Saket Yadav
Area of Interest: STA, VLSI Physical Design, Analog Design, RF-Design, Digital Circuit design, DFT, Memory Design, ASIC. M.Tech in VLSI Design from Guru Gobind Singh Indraprastha University (C-DAC), Delhi Good knowledge in Analog & Digital design circuit concepts. Good understanding of the ASIC design flow Hardware Description Language: Verilog Simulation tools: PrimeTime, Tempus, Cadence(virtuoso), Questa Sim, Graphics PyxisSchematic(eldo), Lynx Design Environment. Programming Languages:Shell scripting, Pyton
Experience
Product Validation Engineer Ii
Dec 2022 — Present
Education
BSEB PATNA
12th, Mathematics, 77.67%
2011 — 2013
Galgotias College of Engineering and Technology
Bachelor of Technology - BTech, Electrical and Electronics Engineering, 70.50%
2014 — 2018
St. Joseph Public School
10th, 9.6 CGPA
2004 — 2011
Guru Gobind Singh Indraprastha University
Master of Technology - MTech, VLSI, 92.7%
2020 — 2022
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