Suresh Rai

About Suresh Rai

Please join me on Self-learning/understanding the details of the interaction of GPU/CPU architecture and software Physical Design, VLSI CAD, and SoC Physical Design. I am pursuing VLSI Physical Design and EDA/CAD tool development expertise. I am a passionate, energetic, and creative thinker who loves to solve problems. I am also a fast learner and strongly want to learn new things.Worked as CAD Engineer at Intel, having previously interned at Mentor Graphics and Robert BoschSkills:• EDA/CAD Tools: Intel Genesys, Mentor Graphics Calibre( DRCd, LVS, PEX), Cadence (Virtuoso), Innovus, Encounter, Cosmoscope, Hspice.• Programming Languages: SKILL, PERL, TCL, C, C++, Unix Shell ScriptsWorked as Trainee in Mentor graphics dealing with “Design and Verification of Electronic Design and System using System Verilog “ ASIC Verification UVM methodology. Worked as an INTERN in Robert Bosch Engineering & Business Solution Limited, India, RBEI as Embedded Application Software Developer (ASW-CRP) in chassis system responsible for Development and Implementation of new Value Added Functions (VAFs) in Active Safety. Languages: Verilog, System Verilog, Perl, TCL, C, C++ Shell scripting, Assembly, Embedded C. Chip worked on: 8051, 8085, ARM7 TDMI,TMS470 and CORTEX M0. Tools:Genesys, Questa Sim, Model Sim, ASCET, MATLAB, Keil3/4, Quartus II, Eagle and LABVIEW. Boards worked on: Nuvoton (arm cortex M0), Altera DE1, ARM 7TDMI, Raspberry pie B model (ARM11 Board), MSP430, CC430.

Experience

1. Staff Engineer Ppa and Feas

   Samsung Semiconductor

   Nov 2022 — Present · Austin, TX, US

   PPA, FEAS and RTL optimizationEnsuring success from initial floor planning through to tape-out and sign-off with across-team collaboration RTL Feedback: Understand the micro-architecture, perform feasibility studies and area sweeps, make frequency, performance, and power trade-offs, and design and balance the pipeline stages.Good understanding of GPU and working alongside Arch and RTL teams.Drive RTL-to-GDSII convergence - synthesis, floor-planning, placement, cts, route, timing closure, and signoff with best PPAFMax push and frequency sweeps, IO budgeting.Enhance and create methodologies and recipes across various implementation steps for the best PPA, VF curve, and Fmax push.

Education

• University of Mumbai

  Bachelor of Engineering (B.E.), Electronics and Telecommunications Engineering

• University of Minnesota

  VLSI Design and Automation

• Thakur College of Science & Commerce

  Science, science

• Vellore Institute of Technology

  Master of Technology - MTech, Embedded and VLSI

Skills

• Arm Cortex-M0
• Automotive
• Arm7
• Systemverilog
• Questa
• Research
• Vhdl
• C++
• Microcontrollers
• Embedded Software
• Unix
• Nuvoton
• Asic
• Linux
• Ascet
• Altera
• Ibm Rational Tools
• Teaching
• Embedded C
• Digital Image Processing
• Posix
• Arm11
• Rtos Vxworks
• Embedded Software Programming
• Robotics
• Object Oriented Design
• Labview
• Cadence Skill
• Tcm
• Zigbee
• Arm Architecture
• Uvm
• Rtos
• Semiconductors
• Rational Doors
• Python
• Digital Designs
• Vlsi
• C
• Programming