Scott J. Bowden

About Scott J. Bowden

I am a results-driven semiconductor engineering leader passionate about optimizing design for test (DFT) strategies, driving efficiency, and delivering high-quality silicon solutions at scale. With extensive experience in silicon design and test methodologies, I have led global teams to improve test quality, reduce costs, and enhance manufacturing yield.Beyond technical excellence, I am deeply committed to developing high-performing teams, fostering innovation, and empowering engineers to excel. I thrive on mentoring and leading global teams, cultivating a culture of continuous learning, collaboration, and problem-solving to drive both individual and organizational success.Throughout my career, I’ve collaborated with cross-functional teams and both internal and external foundries to develop innovative DFT and test solutions—saving millions in test production costs while ensuring the highest silicon quality. My expertise spans silicon design, DFT architecture, test strategy, and cutting-edge AI/ML applications in semiconductor testing.I thrive in dynamic environments where strategic problem-solving, technical leadership, and talent development converge to drive impactful results. Always eager to take on new challenges, mentor teams, and push the boundaries of semiconductor technology, I look forward to connecting and exploring ways to drive innovation together.CAREER HIGHLIGHTSLed efforts to improve silicon designs on external foundries enabling a 20% reduction in test cost and multi-quarter faster external node adoption.Directed AI/ML strategies and silicon design optimizations to save over $250 million annually in test costs. Spearheaded efforts to unify, standardize, and optimize Design for Test across Intel, improving test coverage by several percent and reducing effort by 15%, saving millions of dollars. Selected to relocate internationally, bringing best-known methods to the Israel team and solving scan and multi-die problems, enabling high-quality, on-time designs across three generations. Testified in a court case on behalf of Intel, playing a key role in invalidating the opponent’s patents and saving the company $300 million.Specialties: Engineering Management, Program Management, Global Team Management, RTL design, Logic design, Design for Test, JTAG, ATPG/Scan, Post-Si Test

Experience

1. Senior Principal Cpu Design Engineer

   Aheadcomputing

   May 2025 — Present · Portland, OR, US

Education

• Brigham Young University

  MS, Electrical Engineering

  1998 — 2000

• Brigham Young University

  BS, Computer Engineering

  1992 — 1999

Skills

• Joint Test Action Group (Jtag)
• C
• Jtag
• Atpg
• Processors
• Hardware
• Fpga
• Soc
• Perl
• Verilog
• Testing
• Rtl Design
• Timing
• Dft
• Logic Synthesis
• System on a Chip (Soc)
• Intel
• Static Timing Analysis
• Debugging
• Logic Design