Siva Sankar Agraharapu

About Siva Sankar Agraharapu

SoC front-end RTL design expert with a diversified skill set in both technical and leadership roles. Apart from technical excellence in SoC RTL execution, good at technical coaching, mentoring, interviewing, and stakeholder management skills. Having been an overall 24+ years of successful VLSI domain career.21+ years of Industry experience in the VLSI domain predominantly in the areas of (a) SoC Micro-architecture in Clocking, Power management, NoC/Fabric/Interconnects, high-speed IOs (b) SoC test infrastructure logic feature implementation schemes: JTAG-TAP, BSCAN, Logic SCAN, MBIST, IO Analog DFT.(c) Design and Verification of SoC Functional, Test, Debug, and Characterization features (d) Design Methodologies - RTL Design, Synthesis, STA, FEV, CDC, UPF, Fishtail (e) Expert in defining requirements-based SoC verification plans and reviews (f) Expert in SoC Clocking micro-architecture and power optimization techniques (g) Good in core clocking IP features of foundation blocks Xtal/PLL/RO/CRO/Bandgap etc.(h) Good in subsystem clocking features of Display/Image/Memory/Core infrastructures (i) Hardware/Software interaction for low-power mode flows (j) Skilled in pre-si and post-si debugging3 years of Research experience in VLSI design from IIT Bombay where contributed significantly to industry-collaborated Academic Research projects. In this role contributed to (a) EDA Tool Management / VLSI lab administration (b) Process, device, Layout, Circuit level simulation/Characterization using T-CAD tools (c) Worked on Network IP Lookup Engines (d) Reconfigurable Architectures (e) Teaching Assistant to Graduate/Post-graduate/Research studentsHaving Advanced Diploma certification in VLSI design from VEDA-IIT and training certification in FPGA design, Magma Synthesis tools, Memory VIPs, Wireless protocols etc.Passionate to learn and demonstrate quality.

Experience

1. Sr System-on-chip Design Engineer Soc Fabrics Microarchitect

   Intel

   Jul 2021 — Present · Portland, OR, US

Education

• Sri Vishnu Seva Asram ( Now Ashram Public School) / Maharshi Public School

  Primary School ( LKG to 7th)

  1983 — 1991

• Indian Institute of Technology, Bombay

  Masters, Microelectronics

  2002 — 2004

• Govt. Andhra Polytechnic Kakinada

  DECE, Electronics and Communications

  1994 — 1997

• Govt High School APSP Kakinada

  High School ( 8th-10th)

  1991 — 1994

• Andhra University

  B.E, Electronics

  1997 — 2001

Skills

• Ic
• Hardware
• Pcie
• Asic
• System on a Chip (Soc)
• Electronics
• Vlsi
• Vhdl
• Very-Large-Scale Integration (Vlsi)
• Soc
• Eda
• Rtl Design
• Microprocessors
• Microcontrollers
• Cmos
• Application-Specific Integrated Circuits (Asic)
• Verilog
• Static Timing Analysis
• Functional Verification
• Systemverilog
• Debugging
• Cadence Virtuoso