Siva Kumar Reddy Yadiki
Physical Design Engineer
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Soc Design Engineer
Oct 2022 — Present
Skills
- Windows
- Ic Compiler Ii
- Cadence Spectre
- Upf
- Place and Route
- Fpga Flow
- Spice
- Design Planning and Power Planning
- Asic
- Comsol
- Matlab
- Cts
- Verilog
- Design Compiler
- Xilinx Ise
- Java
- Mixed-Signal Ic Design
- Very-Large-Scale Integration (Vlsi)
- Vhdl
- Vhdl-Ams
- Linux
- Modelsim
- Cadence Encounter
- Digital Electronics
- Starrc
- Cadence Virtuoso Layout Editor
- Synopsys Tools
- Verilog-Ams
- Ic Compiler
- C
- Prime Time
- Physical Verification of Layouts
- Cadence Virtuoso
- Microsoft Office
- Vlsi
- Physical Design
- Cadence Icfb
- Powerpoint
- Asic Design
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