Sivakumar Yabaka

About Sivakumar Yabaka

Intel:Responsibilities including Execute top-level regression in automated mode, investigate and debug defects, elevate issues to designers at SCHEDULING and EXECUTION level of CPUHad good understanding of CPU pipeline structure. Implemented comprehensive test plan and wrote test cases Closely working with RTL design engineers, suggested logic s to fix the issuesSamsung:Worked for bootrom (BL0) validation to make sure Host CPU jump to BL0 address on reset and execute BL0 properly to load BL1 into internal SRAM from external devices UFS, SDMMC, EMMC and USB.Working for verification of Design for Debug(DFD) availability on SOC where I had very good understanding on Coresight, SJTAG, BDU, STM,ATB, TAP and Debug Core. Helped new team members for understanding of bootrom flow and DFD features and for debugging defects.

Experience

1. Staff Engineer

   高通

   Dec 2023 — Present

Education

• Vellore Institute of Technology

  Master of Technology (M.Tech.), VLSI

  2013 — 2015

• Y.S.R engineering college of YVU

  Bachelor of Technology (B.Tech.), Electronic and Communications Engineering

  2009 — 2013

Skills

• Ooo Execution
• Debugging Code
• Modelsim
• Formal Verification
• Systemverilog
• Uvm
• Cpu Scheduling
• Test Cases
• Perl
• • Fpga and Asic Design Implementation.
• Verilog
• Cpu Execution
• Pipelining
• Cpu Design
• Load Store Q
• Functional Verification