Siva Bonasu

About Siva Bonasu

An ASIC Design Lead experienced in SOC, Microarchitecture, Low Power. High Speed Digital Design, DSP, Synthesis, Static Timing Analysis and Physical Design. Design experience includes, but not limited to, Audio/Voice Codec, 4G/5G Modem, DDR Memory Controller Subsystem and DSP algorithm implementation.

Experience

1. Hardware Engineer

   Apple

   Jun 2021 — Present

Education

• Arizona State University

  Master of Science in Engineering, Electrical Engineering - Solid State Electronics

  1999 — 2001

• Jawaharlal Nehru Technological University

  Bachelor of Technology, Electronics and Communications Engineering

  1995 — 1999

Skills

• Asic
• Verilog
• Vhdl
• Digital Signal Processors
• Systemverilog
• Matlab
• Audio Design
• Mixed Signal
• Cmos
• Rtl Design
• Soc
• Dsp
• Digital Communication
• Logic Synthesis
• Semiconductors
• Ic
• Fm
• Vhdl-Ams
• Verilog-a
• Debugging
• Analog
• Primetime
• Static Timing Analysis
• Timing Closure
• Application-Specific Integrated Circuits (Asic)
• Integrated Circuit Design
• Place %26 Route
• Physical Synthesis
• Rtl Development
• Power Analysis
• Power Estimation
• Power Optimization
• Low Power Design
• Synopsys Primetime
• Simvision
• Ncsim
• Rtl Coding
• Microarchitecture