Siva Sankar

senior lead design engineer

Role
Senior Lead Design Engineer at NXP Semiconductors
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

About Siva Sankar

Core skills- ASIC tool flows ( Lint, CDC/RDC, timevison, powerpro, FC & DC, stylus genus by cadence )- RTL design (VHDL/Verilog), FPGA Prototype Development & Debugging- Worked on ZYNQ SOC zedboard for video image processingTools - VIVADO,HLS- fusion compiler & Design compiler - Questa qverify and spyglass - verdi & vcs - powerpro by mentor for power calculation- time vison for timing constraints A focused professional with zeal to make a winning career in Electronic Engineering Semiconductor Industry.Well versed with Design flows in FPGA/ASIC Designing as well as VLSI Designing Tools.Sound understanding of scoping, digital design for requirements gathering & analysis.Instrumental to explore research, development and design related to hardware (Device, Circuit and architecture) on ALTERA & XILINX Development boards.Exposure in RTL coding & debug in design units.A fast learner with excellent problem solving skills. Ability to work accurately and pay attention to details.

Experience

  1. Senior Lead Design Engineer

    NXP Semiconductors

    Jan 2022 — Present · Bengaluru, IN

    Understanding of CARV specifications and requirements.Involved in Design & RTL CodingInvolved in PPA release and Debugging issuesASIC tool flows (CDC/RDC, Lint, Synthesis) Powerpro for power analysis and optimization level in RTL Constraints, amp_sdc checks and Regressions run and debugging it & fixing them.Timing analysis for the paths on logic optimization with some PPA discussion.Wrapper & Integration of Debug & Trace module & RTL coding for core2message block.

Education

  • Jawaharlal Nehru Technological University

    Bachelor's Degree, Electrical, Electronics and Communications Engineering

    2010 — 2014

Skills

  • Soc
  • Electronics
  • I2c
  • Matlab
  • Fpga
  • Soc Zedboard
  • Systemverilog
  • Functional Verification
  • Semiconductors
  • Matlab Hdl Coder
  • Verilog
  • Microsoft Office
  • Vlsi
  • Field-Programmable Gate Arrays (Fpga)
  • Vhdl
  • Rtl Design
  • Very-Large-Scale Integration (Vlsi)
  • Static Timing Analysis
  • Digital Electronics
  • System Verilog
  • Vivado
  • System on a Chip (Soc)
  • Hls Vivado
  • Linux
  • Modelsim

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Siva Sankar — Senior Lead Design Engineer at NXP Semiconductors in Bengaluru, KA, IN | Unifers