Siva Mohan Reddy Chedulla

Senior Staff Analog Engineer @Marvell Technology

San Jose, CA, US
EMAILS
s••••••••@marvell.com
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Apr 2020 — Present

Senior Staff Analog Engineer @Marvell Technology

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Santa Clara, CA, US

As part of clocking team I am responsible for designing feedback dividers, voltage regulators, Phase Interpolator, CML buffers, charge pump and verification of top level performance of analog PLLs. Also responsible for designing CDPHY TX for automotive applications.

EDUCATION

2006 — 2008

National Institute of Technology Warangal

Master of Technology (MTech), VLSI

2002 — 2006

Gayatri Vidya Parishad Engg College

Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

2014 — 2014

Columbia University

Master of Science (MS), Electrical and Electronics Engineering

SKILLS

VerilogMixed SignalCircuit DesignDacAnalog Circuit DesignVhdlCadence VirtuosoIntegrated Circuit DesignVlsiLvsEdaCmos

ABOUT SIVA MOHAN REDDY CHEDULLA

As a member of clocking team at Marvell Technology I am responsible for designing feedback dividers, voltage regulators, Phase Interpolator, CML buffers, charge pump and verification of top level performance of analog PLLs. Also designed CDPHY TX for automotive applications.I worked as an analog and mixed signal design engineer in Texas Instruments for about four and half years. I graduated from Columbia University, New York in December 2014.As an analog design engineer in Texas Instruments, I worked on RC relaxation oscillator design, low power transmitter design( LPTX ), Voltage to Current ( V to I ) reference design, General purpose IO design, level shifter design, analog buffer amplifier design for temperature sensor, buffered DAC design and a LDO to power DC-DC block internally. As a graduate student in Columbia University I designed a 5-bit 100MSPS Flash ADC including the strong arm latch comparator, A fully differential multiply by two switched capacitor Op-amp circuit for a 10-bit 18MSPS pipelined ADC stage.Designed a sampled loop filter based PLL for Bluetooth application at 2.4GHz with channel separation of 1MHz in IBM 90nm technology.Skills: Analog and mixed signal circuit design, MATLAB, Cadence ICFB, Virtuoso, Nanosim, VHDL, VERILOGAreas of Interest: Analog and mixed signal circuit design, ADC, DAC, LDO, OSCILLATORS

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