Sirmad Mahmood Hashmi

Design Verification Engineer @Chipglobe

Munich, DE

Design Verification Engineer | ChipGlobe GmbH (Client: Infineon Technologies AG, Munich, Germany)I am part of the FB-level verification team working on a microcontroller project, with a primary focus on formal verification and gradually transitioning into simulation-based verification.My day-to-day work involves using Cadence JasperGold apps—including Connectivity (ConnApp), Functional Verification Planning (FVP), and Coverage Verification (CovV)—to validate RTL designs against specifications using formal methods. I have contributed to the development of an automated property generation tool to support scalable and reusable formal verification methodologies.Additionally, I helped enhance the formal verification subflow by developing formal wrappers for project setup and resource automation. I have also served as an application engineer for vManager, supporting formal regression execution and debug.I recently completed SystemVerilog and UVM training (Doulos) to broaden my capabilities in functional verification. I hold a degree in Computer Science and have strong interests in AI, NLP, and data-driven automation in the verification domain.Core Competencies:*) Formal Verification (Cadence JasperGold: ConnApp, FVP, CovV, Property Generator)*) SystemVerilog (Assertions, SVA, UVM – Beginner, Doulos Certified)*) FB-Level Microcontroller Verification*) RTL Design Understanding & Functional Safety*) Scripting & Automation: Python, Robot Framework*) Tools & Platforms: Linux (RHEL), Git, Jira, ClearCaseAdditional Skills:Data Mining, Machine Learning (Pandas, NumPy, Scikit-learn, RapidMiner), NLPPublication:S. M. Hashmi, “Comparative Sentiment Analysis: Great Britain versus the United States of America using Ensemble Methods,” MESTERSÉGES INTELLIGENCIA, vol. 2020, no. 1, pp. 45–53, 2020.[Online]. Available: https://real-j.mtak.hu/14265/1/MI_2020_1.pdf