Sirisha Nalmela

About Sirisha Nalmela

15+ years of experience in high-performance and low-power ASIC design process, from architecture, documentation, RTL coding and verification, embedded assertions, functional coverage, synthesis, timing closure, and tapeout. Specialties: Digital VLSI Design (RTL level for both ASIC and FPGA), Design-for-Verification, High level synthesis, Place and Route, ASIC Verification (UVM Methodology), Electronic Design Automation, Scripting (TCL, Perl, Python), Verilog, VHDL, Xilinx ISE, Altera Quartus, C, Java

Experience

1. Principal Engineer

   Marvell Technology

   Mar 2019 — Present · Marlborough, MA, US

Education

• Dhirubhai Ambani Intitute for Information and Communication Technology

  B.Tech, ICT

  2002 — 2006

• International Institute of Information Technology Hyderabad (IIITH)

  MS by Research, VLSI and Embedded Systems

  2007 — 2009

• University of Pennsylvania

  MS, Electrical Engineering

  2010 — 2011

Skills

• Logic Synthesis
• Design for Verification
• Very-Large-Scale Integration (Vlsi)
• C++
• Xilinx Ise
• Altera Quartus
• High Level Synthesis, Place and Route
• Altera
• Functional Verification
• Verilog
• Integrated Circuit Design
• Microprocessors
• Computer Architecture
• Rtl Design
• Static Timing Analysis
• Python
• Java
• Shell Scripting
• Field-Programmable Gate Arrays (Fpga)
• Perl
• Embedded Systems
• Eda
• Fpga
• Application-Specific Integrated Circuits (Asic)
• Asic
• Vlsi Design (Asic and Fpga)
• Tcl
• C
• Vlsi
• Modelsim
• Digital Design
• Vhdl