Sireesha Chevvu

About Sireesha Chevvu

Silicon Design Engineer with expertise in developing and refining static design tools (CDC, RDC, Lint, VCLP) and a good understanding of low-power design techniques and SoC Reset Architecture. Skilled in resolving static check issues and collaborating with cross-functional teams to enhance design quality and efficiency.As an Associate Staff Engineer at Samsung Semiconductor India Research, I contributed to the ISP IP RTL design for Exynos, Samsung\'s flagship mobile SoC. My work included designing the microarchitecture for key modules of the HDR10+ IP for cameras and implementing geometric distortion correction for mobile cameras. I also led critical signoff checks, including CDC, DFT, lint closure, SFR simulations, and IPXACT, utilizing tools like Git and Verdi to ensure robust design quality.Prior to Samsung, as an ASIC Design Engineer at Soctronics, I played a pivotal role in designing AI-based IPs with TSMC 22nm libraries. My responsibilities ranged from developing glue logic for AXI interface integration to designing sub-IPs for LL component computation using wavelet decomposition. Additionally, I performed timing analysis across various frequencies and addressed key challenges such as bug fixes, IPXACT, lint, and synthesis.Passionate about IP design, I am driven to create innovative, efficient, and optimized solutions in ASIC IP design, combining technical expertise with a dedication to delivering impactful results.

Experience

1. Senior Technical Lead

   HCLTech

   Oct 2025 — Present · Omaha, NE, US

   Working for ARM as a contractor

Education

• Sree Vidyanikethan Engineering College

  Bachelor of Engineering - BE, Electronics and Communications Engineering