Jatinder Singh
- Role
- Asic & Fpga Design Engineer at Meta
- Location
- Menlo Park, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jatinder Singh
Experienced RTL Design Engineer with a demonstrated history of working in the…
Experience
Asic & Fpga Design Engineer
Mar 2019 — Present
Education
Indian Institute of Technology, Madras
B. Tech, Electrical Engineering
2002 — 2006
UC San Diego
MS, Computer engg
2010 — 2012
Skills
- Integrated Circuit Design
- Asic
- Rtl Design
- Digital Signal Processors
- Debugging
- Arm Architecture
- Static Timing Analysis
- Matlab
- Vlsi
- Systemverilog
- Functional Verification
- Verilog
- Soc
- Very-Large-Scale Integration (Vlsi)
- Application-Specific Integrated Circuits (Asic)
- Arm
- C
- Eda
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