Sind B
Analog Layout Engineer at Capgemini
- Role
- Tsmc - Analog Layout Engineer at Capgemini
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sind B
Total 2+ Years of IT experience as an Analog Layout Design Engineer. Experience in Technologies: TSMC - 2nm, Intel - 5nm, 7nm, 16nm, 10nm, 22nm, 28nm. Have experience in TSMC 2nm technology [worked on different blocks in LJPLL & DLVR blocks from starch level floorplan to LVS, DRC Cleanup. Have experience in HBM3 Project on 10nm technology [ worked on Local tree blocksfrom starch level floorplan to LVS, DRC Cleanup. Have experience in DDR Project on 7nm (1276) technology [ worked on PhysicalVerification Check\'s hipallf Flows] Have experience in Acphy Project on 5nm (1278) technology [worked on op-amp block from scratch level floorplan to LVS, DRC Cleanup. Have experience in 16nm,22nm,28nm [ worked on DRC checks] Experience on developing the Analog Layout\'s and understanding flow of the design. Experience on Layout Concepts Means Failure Mechanisms: Crosstalk, latch up, IR drop, EMIR, Antenna Effect, Matching techniques, Routing, Shielding.etc. Good experience on Bundle flow check’s – hipallf. Familiar with tools: Cadence, virtuoso, caliber. Good experience in Auto place Route [APR] by using automation tool for analog blocksin lower technology node 2nm.
Experience
Tsmc - Analog Layout Engineer
Apr 2024 — Present · Hyderabad, IN
Present working on TSMC -3nm Project Experience on TSMC -2nm Project
Education
Malla Reddy College of Engineering & Technology
Master of Technology , VLSI & Embedded
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