Sima Kumari

About Sima Kumari

I am a fresher, graduated from M. Tech from the National Institute of Technology, Durgapur in ECE.I am a block-level designer. I have a good understanding of RTL-to-GDS flow.Post-Synthesis Analysis: Running experiments in Optimising critical paths using various optimization techniques used in the Design Compiler Synthesis Tool.•Analysing the timing reports and fixing for false paths, max paths, min paths, multi-cycle paths, asynchronous clocks, etc in post-synthesis.• Finding the issues of Increasing Logical depth, Max fanout, Upsizing, Pipelining, etc.• Routing Congestion, Placement Congestion, defining fencing regions, placement and routing blockages.•Fixing Placement DRCs, Routing DRCs, Shorts, DRV violations, applying NDRs for CTS and critical nets in CAD tool ICC2.•Performed setup checks, hold checks for analysis, Fixed setup violations, promoted critical nets to higher metal layers, buffer insertion, clock gating checks, etc.•Understanding sdc constraints, experimental runs based on SDCs with a focus on performance.• Achieved better timing closure in many sub-hierarchies.

Experience

1. Design Engineer Ii

   铿腾设计系统公司

   Sep 2025 — Present · Noida, IN

Education

• Oriental Institute of Science & Technology, Thakral Nagar, Opp Patel Nagar, Raisen Road, Bhopal-462021

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2017 — 2021

• National Institute of Technology Durgapur

  Master of Technology - MTech