Sijo P K

About Sijo P K

Experienced IP Verification Lead with a strong background in verification methodologies, testbench development, and coverage closure for advanced SoCs and IPs. Proven expertise in leading verification teams, delivering high-quality results, and ensuring robust design validation. Skilled in SystemVerilog, UVM, and end-to-end functional verification.Professional ExperienceIP Verification Lead | IntelMay 2021 – PresentSpearheading the verification efforts for 5G and RF IPs, managing a team of skilled verification engineers.Driving the development and execution of Verification Plans, Test Plans, and Functional Coverage Documentation.Architected and implemented SV-UVM Testbenches to support advanced verification environments.Responsible for Functional Verification including test case development and functional coverage bring-up.Developed and implemented SystemVerilog Assertions to enhance verification rigor.Performed regression debugging and achieved 100% regression and code coverage closure, ensuring robust design validation.SoC Verification Engineer | Microchip TechnologyJan 2018 – April 2021Conducted block-level verification of complex SoC components, with a focus on MPU verification.Successfully brought up testbenches, developed SystemVerilog Assertions, and achieved comprehensive coverage goals.Performed regression debugging, ensuring high-quality design verification across multiple projects.Technical SkillsProtocol ExpertiseAXI4, APB, I2C, SPIProgramming and Verification LanguagesVerilog, SystemVerilog (SV), UVM (Universal Verification Methodology)ScriptingPerl for automation and productivity in verification environments

Experience

1. Verification Lead

   Intel

   May 2021 — Present · Bangalore Urban, IN

   IP Verification

Education

• Rajiv Gandhi Institute of Technology, Kottayam

  M. Tech, Advanced Electronics and Communication

  2014 — 2016